/* Define Register Locations for C Portion of code */

#define REG_BASE 0x1000

#define PORTA   REG_BASE+0x000
#define PIOC    REG_BASE+0x002
#define PORTC   REG_BASE+0x003
#define PORTB   REG_BASE+0x004
#define PORTCL  REG_BASE+0x005
#define DDRC    REG_BASE+0x007
#define PORTD   REG_BASE+0x008
#define DDRD    REG_BASE+0x009
#define PORTE   REG_BASE+0x00A
#define CFORC   REG_BASE+0x00B
#define OC1M    REG_BASE+0x00C
#define OC1D    REG_BASE+0x00D
#define TCNT    REG_BASE+0x00E
#define TIC1    REG_BASE+0x010
#define TIC2    REG_BASE+0x012
#define TIC3    REG_BASE+0x014
#define TOC1    REG_BASE+0x016
#define TOC2    REG_BASE+0x018
#define TOC3    REG_BASE+0x01A
#define TOC4    REG_BASE+0x01C
#define TOC5    REG_BASE+0x01E
#define TCTL1   REG_BASE+0x020
#define TCTL2   REG_BASE+0x021
#define TMSK1   REG_BASE+0x022
#define TFLG1   REG_BASE+0x023
#define TMSK2   REG_BASE+0x024
#define TFLG2   REG_BASE+0x025
#define PACTL   REG_BASE+0x026
#define PACNT   REG_BASE+0x027
#define SPCR    REG_BASE+0x028
#define SPSR    REG_BASE+0x029
#define SPDR    REG_BASE+0x02A
#define BAUD    REG_BASE+0x02B
#define SCCR1   REG_BASE+0x02C
#define SCCR2   REG_BASE+0x02D
#define SCSR    REG_BASE+0x02E
#define SCDR    REG_BASE+0x02F
#define ADCTL   REG_BASE+0x030
#define ADR1    REG_BASE+0x031
#define ADR2    REG_BASE+0x032
#define ADR3    REG_BASE+0x033
#define ADR4    REG_BASE+0x034
#define OPTION  REG_BASE+0x039
#define COPRST  REG_BASE+0x03A
#define PPROG   REG_BASE+0x03B
#define HPRIO   REG_BASE+0x03C
#define INIT    REG_BASE+0x03D
#define TEST1   REG_BASE+0x03E
#define CONFIG  REG_BASE+0x03F

/* Define Register Locations for ASM Portion of Code */

#asm
REG_BASE        equ     $1000

PORTA           equ     REG_BASE+$0000
PIOC            equ     REG_BASE+$0002
PORTC           equ     REG_BASE+$0003
PORTB           equ     REG_BASE+$0004
PORTCL          equ     REG_BASE+$0005
DDRC            equ     REG_BASE+$0007
PORTD           equ     REG_BASE+$0008
DDRD            equ     REG_BASE+$0009
PORTE           equ     REG_BASE+$000A
CFORC           equ     REG_BASE+$000B
OC1M            equ     REG_BASE+$000C
OC1D            equ     REG_BASE+$000D
TCNT            equ     REG_BASE+$000E
TIC1            equ     REG_BASE+$0010
TIC2            equ     REG_BASE+$0012
TIC3            equ     REG_BASE+$0014
TOC1            equ     REG_BASE+$0016
TOC2            equ     REG_BASE+$0018
TOC3            equ     REG_BASE+$001A
TOC4            equ     REG_BASE+$001C
TOC5            equ     REG_BASE+$001E
TCTL1           equ     REG_BASE+$0020
TCTL2           equ     REG_BASE+$0021
TMSK1           equ     REG_BASE+$0022
TFLG1           equ     REG_BASE+$0023
TMSK2           equ     REG_BASE+$0024
TFLG2           equ     REG_BASE+$0025
PACTL           equ     REG_BASE+$0026
PACNT           equ     REG_BASE+$0027
SPCR            equ     REG_BASE+$0028
SPSR            equ     REG_BASE+$0029
SPDR            equ     REG_BASE+$002A
BAUD            equ     REG_BASE+$002B
SCCR1           equ     REG_BASE+$002C
SCCR2           equ     REG_BASE+$002D
SCSR            equ     REG_BASE+$002E
SCDR            equ     REG_BASE+$002F
ADCTL           equ     REG_BASE+$0030
ADR1            equ     REG_BASE+$0031
ADR2            equ     REG_BASE+$0032
ADR3            equ     REG_BASE+$0033
ADR4            equ     REG_BASE+$0034
OPTION          equ     REG_BASE+$0039
COPRST          equ     REG_BASE+$003A
PPROG           equ     REG_BASE+$003B
HPRIO           equ     REG_BASE+$003C
INIT            equ     REG_BASE+$003D
TEST1           equ     REG_BASE+$003E
CONFIG          equ     REG_BASE+$003F
#endasm